NDLI: Thin oxide reliability

Content Provider	IEEE Xplore Digital Library
Author	Chenming Hu
Copyright Year	1985
Description	Author affiliation: University of California, Berkeley, California (Chenming Hu)
Abstract	Dielectric breakdown and oxide and interface charge trapping set the scaling limits for thin oxides. Oxide leakage is far from being the limit. Dielectric breakdown is modeled by hole trapping at "weak" sites with local, above-average current density or large hole trap density. This model predicts a linear relationship between in tBDand 1/F rather than E. It provides a framework for predicting oxide reliability as a function of area and stress condition from limited data. Using this model and the field experience of thin-oxide EEPROM, it is estimated that 0.01% failure per thousand hour is achievable with 9.5 nm oxides at 5V. This is adequate for 1M-bit DRAMs. Charge trapping and interface trap generation sets slightly less restrictive limit for gate oxides. "Defect" reduction holds promise for improving oxide reliability. New dielectrics will probably be necessary at 4M-bit level unless 10 $µm^{2}capacitors$ are available or cell operation is changed. 6.5 nm oxide should be acceptable for 3.3V operation. Again EEPROMs will provide the real-life test for production thin oxide at that thickness.
Starting Page	368
Ending Page	371
File Size	354941
Page Count	4
File Format	PDF
DOI	10.1109/IEDM.1985.190977
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electron traps Dielectric breakdown Electric breakdown Capacitors Current density Predictive models Testing Random access memory EPROM Tunneling
Content Type	Text
Resource Type	Article

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