NDLI: Low noise single and dual gate D-MOS transistor

Content Provider	IEEE Xplore Digital Library
Author	Sigg, H.J. Vendelin, G.D.
Copyright Year	1972
Description	Author affiliation: Signetics Corporation, Sunnyvale, California (Sigg, H.J.)
Abstract	Several reports have been published on modeling the noise behavior of MOSFETs in the very-high and ultra-high frequency range. These devices showed considerable excess noise which is reflected in too high values of noise resistance Rncompared to the theoretical thermal noise limit. This report shows that at high enough frequencies the theoretical value of noise resistance (75Ω at 2 GHz) can be observed on a new kind of MOSFET called D-MOS. Measured minimum noise figures are 3.4 dB at 1 GHz and 5.1 dB at GHz for single gate devices. Noise resistance, minimum noise figure, optimum source admittance and available gain have been calculated as a function of frequency from 0.1 - 2.0 GHz for a single gate and a dual gate D-MOS structure. The results are compared to measurements, some of them made in other labs for correlation. The measurements lead to the conclusion that the thermal noise sources are sufficient to describe the noise behavior of D-MOS at high enough frequencies while at the lower frequencies the theoretical minimum noise figures could not be fully realized due to difficulties in the measurement techniques and possibly additional noise sources.
Starting Page	26
Ending Page	26
File Size	93492
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1972.249245
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1972-12-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise figure MOSFETs Electrical resistance measurement Thermal resistance Noise measurement Admittance Frequency measurement Measurement techniques
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Modelling of the double-diffused MOST's with self-aligned gates

An additional contribution in the noise spectrum of SOI MOSFETs

Channel Noise Current in Deep Sub-Micron MOSFETs

The minimum noise figure and mechanism as scaling RF MOSFETs from 0.18 to 0.13 /spl mu/m technology nodes

Strain-induced very low noise RF MOSFETs on flexible plastic substrate

A high-frequency representation of the MOS transistor

Modeling of low-frequency noise in single- and double-gate MOSFETs using quantum mechanical approach

Experimental Validation of Simple Electro-Thermal Circuit Models for SOI MOSFETs by Direct DC-UHF Measurement of Drain Admittance

The frequency response of bipolar transistor noise figure

Low noise single and dual gate D-MOS transistor

Similar Documents

Modelling of the double-diffused MOST's with self-aligned gates

An additional contribution in the noise spectrum of SOI MOSFETs

Channel Noise Current in Deep Sub-Micron MOSFETs

The minimum noise figure and mechanism as scaling RF MOSFETs from 0.18 to 0.13 /spl mu/m technology nodes

Strain-induced very low noise RF MOSFETs on flexible plastic substrate

A high-frequency representation of the MOS transistor

Modeling of low-frequency noise in single- and double-gate MOSFETs using quantum mechanical approach

Experimental Validation of Simple Electro-Thermal Circuit Models for SOI MOSFETs by Direct DC-UHF Measurement of Drain Admittance

The frequency response of bipolar transistor noise figure

Low noise single and dual gate D-MOS transistor