NDLI: Design considerations of hyper-abrupt tuning diodes

Content Provider	IEEE Xplore Digital Library
Author	Kannam, P.J. Ponczak, S. Olmstead, J.
Copyright Year	1969
Description	Author affiliation: RCA Electronic Components, Somerville, N. J. (Kannam, P.J.)
Abstract	The voltage variable capacitor promises to be an ideal device for electronic tuning applications. For the best design, the capacitance ratio and the quality factor of the devices should be kept as high as possible over the required voltage range. Furthermore, applications requiring more than one diode generally necessitate that the diodes track each other over the useful operating voltage range. When a high capacitance ratio is desired, it is usually achieved by the formation of a hyper-abrupt junction with a retrograded doping profile on one side. The slope and the doping of the retrograded region as well as the thickness of the high resistivity epitaxial region are the critical parameters determining the device characteristics. A knowledge of the interdependence of these parameters is of fundamental importance for the optimization of the design. This paper describes the computer calculation done for the design of tuning diodes. A hyper-abrupt junction with a retrograded Gaussian profile is considered. The computation consists in establishing the doping profile across the wafer with given values of surface concentration, junction depth and epitaxial background doping. The applied voltage as a function of depletion width is determined and the corresponding junction capacitance evaluated. The quality factor as given by the series resistance is then calculated, taking into account the nonlinear variation of mobility with impurity distribution. The breakdown voltage is computed from the field intensity distribution across the junction and the corresponding impact ionization rate. Calculations are carried out over a wide range of device parameters. The various factors that should be considered for an ideal design are discussed.
Starting Page	140
Ending Page	140
File Size	97622
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1969.188190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1969-10-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Diodes Voltage Capacitance Doping profiles Q factor Capacitors Conductivity Design optimization Surface resistance Impurities
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in