NDLI: The insulated-gate field-effect transistor

Content Provider	IEEE Xplore Digital Library
Author	Heiman, F.P. Hofstein, S.R.
Copyright Year	1962
Description	Author affiliation: RCA Laboratories, Princeton, New Jersey (Heiman, F.P.)
Abstract	Some theoretical characteristics of the "Insulated-Gate Field-Effect Transistor" are discussed and the results compared with experimental units that have recently been fabricated. These units consist of a control electrode insulated from a thin conducting channel in the surface of a silicon substrate by an oxide film, as compared to the conventional reverse biased p-n junction unipolar transistor gate. The use of an insulated type gate yields several important advantages, viz: 1. Transistors may be fabricated in which the mechanism of control is either depletion of channel charge, enhancement of channel charge, or a combination of both, providing freedom in circuit design. 2. The continuous transfer characteristic from the negative gate-bias region to the positive bias region allows operation at zero bias. 3. The oxide thickness provides a new design parameter; the thicker oxide units operate at higher speed and power level. 4. Gate leakage current is extremely low; time constant measurements yield an input resistance of $10^{+13}-$ $10^{+16}ohms.$ Units fabricated to date have the following typical characteristics: Input Impedance: 7µµf, $10^{+15}ohms$ Transconductance: 2800 µohms Cut-off bias: -8 volts (depletion unit) Rise Time: 10 nanoseconds (10% - 90 %) The planar construction of these zero junction devices coupled with their highly uniform characteristics have yielded great promise for integrated circuit applications. Progress made toward integrating these elements into large scale logic arrays on a single crystal semiconductor substrate is discussed.
Starting Page	58
Ending Page	58
File Size	58612
Page Count	1
File Format	PDF
DOI	10.1109/IEDM.1962.187313
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1962-10-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Insulation FETs Substrates Logic arrays Electrodes Silicon Conductive films Semiconductor films P-n junctions Circuit synthesis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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