NDLI: Modeling of realistic on-chip power grid using the FDTD method

Content Provider	IEEE Xplore Digital Library
Author	Jinseong Choi Lixi Wan Swaminathan, M. Beker, B. Master, R.
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Jinseong Choi; Lixi Wan; Swaminathan, M.; Beker, B.; Master, R.)
Abstract	In this paper, a multi-layered on-chip power distribution network has been modeled using the finite difference time domain (FDTD) method. This simulation consists of 0.5 million passive elements, 40000 distributed current sources and multiple C4 vias. In this method, a branch capacitor has been used, which is different from latency insertion method (LIM). The use of the branch capacitor is important for simulating multi-layered power grids. The current in the branch capacitor is extracted from Kirchhoffs current law. This provides a good model of the branch capacitor and does not require companion models during simulation. The proposed model has been verified with SPICE through a simple example. The on-chip power grid simulation, the characteristics of noise propagation and the effectiveness of on-chip decoupling capacitors have been discussed. Also the importance of the nonlinearity in the computation of the power supply noise in on- chip power grid has been addressed through the peak noise analysis using linear current source and clock distribution network.
Starting Page	238
Ending Page	243
File Size	436439
Page Count	6
File Format	PDF
ISBN	0780372646
DOI	10.1109/ISEMC.2002.1032481
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power grids Finite difference methods Capacitors Computational modeling Network-on-a-chip Power systems Time domain analysis Delay Kirchhoff's Law SPICE
Content Type	Text
Resource Type	Article

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