NDLI: Challenges and solutions for next generation main memory systems

Content Provider	IEEE Xplore Digital Library
Author	Joong-Ho Kim Dan Oh Kollipara, R. Wilson, J. Best, S. Giovannini, T. Shaeffer, I. Ching, M. Chuck Yuan
Copyright Year	2009
Description	Author affiliation: Rambus Inc., 4440 El Camino Real, Los Altos, CA 94022 (Joong-Ho Kim; Dan Oh; Kollipara, R.; Wilson, J.; Best, S.; Giovannini, T.; Shaeffer, I.; Ching, M.; Chuck Yuan)
Abstract	Today's high performance computing memory systems mainly consist of with DDR3 DRAMs offering 800Mb/s to 1600Mb/s data rates. Extending the performance of these main memory systems beyond the current data rate is quite challengeable as the signal integrity issues with physical channel remains relatively constant compared to the device performance which improves as process advances. This paper presents three key technologies which help the current memory architecture to reach the data rates of 1600~3200Mb/s without sacrificing memory capacity, increasing power consumption, or switching to more advanced differential signaling. These key features include FlexPhase™ timing adjustment to eliminate trace length matching, dynamic point-to-point signaling to increase memory capacity at high data rates, and near ground signaling to reduce IO signaling power. This paper demonstrates the benefits of these features from signal and power integrity point of view.
Starting Page	93
Ending Page	96
File Size	1547270
Page Count	4
File Format	PDF
ISBN	9781424444472
DOI	10.1109/EPEPS.2009.5338468
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Crosstalk Random access memory Routing Logic Analytical models Delay Sampling methods High performance computing Signal processing
Content Type	Text
Resource Type	Article

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