NDLI: Distributed circuit models for near-CSP interconnects

Content Provider	IEEE Xplore Digital Library
Author	Chandrasekhar, A. Beyne, E. De Raedt, W. Nauwelaers, B.
Copyright Year	2002
Description	Author affiliation: Departement Elektrotechniek, Katholieke Univ., Leuven, Belgium (Chandrasekhar, A.; Beyne, E.; De Raedt, W.; Nauwelaers, B.)
Abstract	At frequencies beyond 1 GHz, there is a large difference between the on-chip and off-chip performance, since the package behaves as a passive element and influences the electrical behaviour. An accurate model of the package is necessary to predict this off-package behaviour and it serves as an input to the chip designer for 'chip-package co-design'. However, this is not the only requirement from the model. With chip scale packages being re-designed for different RF applications, the package model is expected to accommodate the variable physical dimensions as model parameters - in other words, be scalable. Several papers in the literature use simple and complex lumped element models to represent package interconnections (Z. Yang et al, WESCON/'95, pp. 106-110, 1995; M.F. Caggiano et al, Proc. 48th IEEE ECTC, pp. 1280-1285, 1998) but there are a number of simple distributed models as well (C.Y. Chung, Proc. 47th IEEE ECTC, pp. 304-309, 1997). However, H. Liang et al (Microwave Symp. Dig., IEEE MTT-S Int., vol. 1, pp. 65-68, 2000) proposed a preliminary "hybrid circuit model" for the BGA transition. For lumped element models, apart from suffering from loss of accuracy at high frequencies, it is almost impossible to study the effect of individual components in the overall package interconnect. In this work, we have developed distributed circuit models for two near-CSPs, namely the polymer stud grid array (PSGA) and the ball grid array (BGA). The differences in the model topology are due to the approaches used for the package routing and consequently the mode of signal propagation. Apart from achieving excellent accuracy up to 8 GHz, both the models can be scaled for changes in the physical dimensions of the package interconnect.
Sponsorship	IEEE Microwave Theory & Techniques Soc. IEEE Components, Packaging & Manuf. Technol. Soc
Starting Page	63
Ending Page	66
File Size	370308
Page Count	4
File Format	PDF
ISBN	0780374517
DOI	10.1109/EPEP.2002.1057884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Radio frequency Semiconductor device measurement Testing Probes Substrates Chip scale packaging Routing Uniform resource locators Scalability
Content Type	Text
Resource Type	Article

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