NDLI: Packaging and interconnect design and analysis using FDTD

Content Provider	IEEE Xplore Digital Library
Author	Piket-May, M. Thomas, K. Gravrok, R.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA (Piket-May, M.)
Abstract	This paper presents information about the development of a versatile FDTD solver and explores design issues relevant to the packaging and interconnect design engineers. The EM analysis development is called "LC". It consists of a GUI interface with the ability to auto-mesh a graphically defined user geometry. A number of different excitations are possible, and the outputs can yield not only field data, but also voltages, currents, impedances, inductances, capacitances and fluxes. Further, both time and frequency-domain data are available on output. It also allows for 2-D visual simulations of the full 3-D problem being simulated during time-stepping. This is very useful in identifying problem areas with a particular design. Another very important and relevant feature of the LC tool is an interface to SPICE which will analyze a circuit based on FDTD field values linked to SPICE at each time step. The SPICE interface also generates output voltages and/or currents that modify the FDTD field values which are then used during the next FDTD time-step. Essentially LC is an integrated EM model editor, simulator, and analysis tool. It is composed of 100,000 lines of C and Fortran, uses OSF/Motif, and is portable to all commercial Unix platforms. Its companion batch simulator, FDTD, and plotting program, LCPlot, are also included in the executable distribution.
Starting Page	87
Ending Page	90
File Size	370386
Page Count	4
File Format	PDF
ISBN	0780386493
DOI	10.1109/EPEP.1997.634045
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packaging Finite difference methods Time domain analysis Circuit simulation SPICE Integrated circuit interconnections Voltage Design engineering Graphical user interfaces Geometry
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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