NDLI: Awards

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2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2014

2013 35th Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012

EOS/ESD Symposium Proceedings

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010

2009 31st EOS/ESD Symposium

EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium

2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

2006 Electrical Overstress/Electrostatic Discharge Symposium

2005 Electrical Overstress/Electrostatic Discharge Symposium

2004 Electrical Overstress/Electrostatic Discharge Symposium

General Chair's welcome

Table of contents

Electromagnetic field induced degradation of magnetic recording heads in a GTEM cell

Wire bonding tip study for extremely ESD sensitive devices

Soft ESD phenomena in GMR heads in the HDD manufacturing process

Nano-transient current and transient resistance on the conductive or dissipative materials for extremely sensitive devices

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits

Low-voltage diode-configured sige:C HBT triggered ESD power clamps using a raised extrinsic base 200/285 GHz (fT/fMAX) SiGe:C HBT device

From the ESD robustness of products to the system ESD robustness

Evaluation of ESD hardness for fingerprint sensor LSIs

Induced ESD on metal object with a small air gap

Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

Study of CDM specific effects for a smart power input protection structure

Implementation of 60V tolerant dual direction ESD protection in 5V BiCMOS process for automotive application

ESD protection design using a mixed-mode simulation for advanced devices

Gate oxide failures due to anomalous stress from HBM ESD testers

Formation and suppression of a newly discovered secondary EOS event in HBM test systems

The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps

Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps

Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product

ESD design automation for a 90nm ASIC design system

ESD induced latent defects in CMOS ICs and reliability impact

CDM failure modes in a 130nm ASIC technology

Compliance verification: The critical component of a certified ANSI/ESD S20.20 ESD control program plan

Notes on maintaining sub-1V balance of an ionizer

CPM study: Discharge time and offset voltage, their relationship to plate geometry

Humidity effects on laminated ESD work surface resistance and charge dissipation properties

Study of “hot spots” arising from non-homogeneity in the micro-structures of dissipative materials

Characterizing automated handling equipment using discharge current measurements

Electrostatic field limits and charge threshold for field induced damage to voltage susceptible devices

Distributed gate ESD network architecture for inter-power domain signals

ESD protection for SOI technology using an under-the-box (substrate) diode structure

Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection

Advanced ESD rail clamp network design for high voltage CMOS applications

ESD protection solutions for high voltage technologies

Development strategy for TLU-robust products

Using coupled transmission lines to generate impedance-matched pulses resembling charged device model ESD

Multilevel Transmission Line Pulse (MTLP) tester

Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations

Improved wafer-level VFTLP system and investigation of device turn-on effects

VF-TLP systems using TDT and TDRT for kelvin wafer measurements and package level testing

Breakdown behavior of TMR head in ESD transients

Effects of ESD transients on noise in tunneling recording heads

Comparison of thermal response of GMR sensor subjected to HBM and CDM transients

Electrostatic discharge (ESD) protection of giant magneto-resistive (GMR) recording heads with a silicon germanium technology

Dynamic temperature rise of shielded MR sensors during simulated electrostatic discharge pulses of variable pulse width

Improvement of ESD robustness and magnetic stability by structure of GMR head

Workshop and panel discussions

History of the EOS/ESD symposium

27th Annual EOS/ESD Symposium!

Call for papers

2003 Electrical Overstress/Electrostatic Discharge Symposium

2002 Electrical Overstress/Electrostatic Discharge Symposium

2001 Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476)

Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396)

Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347)

Proceedings Electrical Overstress/Electrostatic Discharge Symposium

1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

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Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

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03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in