NDLI: ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

Content Provider	IEEE Xplore Digital Library
Author	Mergens, M.P.J. Wilkening, W. Kiesewetter, G. Mettler, S. Wolf, H. Hieber, J. Fichtner, W.
Copyright Year	2000
Description	Author affiliation: Sarnoff Corp., Princeton, NJ, USA (Mergens, M.P.J.)
Abstract	An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.
Starting Page	446
Ending Page	455
File Size	937884
Page Count	10
File Format	PDF
ISBN	1585370185
DOI	10.1109/EOSESD.2000.890115
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	EOS/ESD Association, Inc.
Subject Keyword	Circuit simulation Parasitic capacitance Breakdown voltage Thumb Wiring Delay Driver circuits Electrical resistance measurement Semiconductor device modeling Stress
Content Type	Text
Resource Type	Article

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