NDLI: An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

Content Provider	IEEE Xplore Digital Library
Author	Smith, J.C.
Copyright Year	1999
Description	Author affiliation: Somerset Design Center, Motorola Inc., Austin, TX, USA (Smith, J.C.)
Abstract	In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 /spl mu/m, 35 /spl Aring//70 /spl Aring/ dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over nonSI and SI I/O pad designs, respectively.
Starting Page	62
Ending Page	69
File Size	910569
Page Count	8
File Format	PDF
ISBN	158637007X
DOI	10.1109/EOSESD.1999.818991
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuits CMOS technology Electrostatic discharge Impedance Earth Observing System Voltage MOS devices Transmission lines Robustness Stress
Content Type	Text
Resource Type	Article

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