NDLI: The correlation between latch-up phenomenon and other failure mechanisms

Content Provider	IEEE Xplore Digital Library
Author	Mahanpour, M. Morgan, I.
Copyright Year	1995
Description	Author affiliation: Adv. Micro Devices Inc., Sunnyvale, CA, USA (Mahanpour, M.; Morgan, I.)
Abstract	A previous study by L. G. Henry et al. (see Proceedings 20th ISTFA, Los Angeles, p. 117-26, Nov. 1994) considered in detail an early die revision of a CMOS logic product fabricated using an N-well technology, that showed a higher than expected rate of EOS failure during burn-in and for customer field returns. It was shown that the use of a specific laboratory model simulator can most often replicate a failure signature, i.e., a unique damage morphology and die location associated with a real product failure. A "nondestructive" failure signature induced by Transient Latch-Up (TLU) was described and is studied here in more detail. Five different failure mechanisms were found in the area where Latch-Up (LU) was located by emission microscopy: fusing of the V/sub cc/ metal-bus, metal-metal shorts, metal-poly shorts, gate oxide defects, and a carrier storage effect. This study shows that 90% of all defects identified were within or in close proximity to the latch-up sites. These several failure mechanisms and their relation to LU are discussed.
Starting Page	289
Ending Page	294
File Size	943965
Page Count	6
File Format	PDF
ISBN	1878303597
DOI	10.1109/EOSESD.1995.478296
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Failure analysis CMOS logic circuits CMOS technology Earth Observing System Laboratories Semiconductor device modeling Morphology Microscopy
Content Type	Text
Resource Type	Article

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