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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sengupta, A. Sedaghat, R. |
| Copyright Year | 2015 |
| Description | Author affiliation: Electr. & Comput. Eng., Ryerson Univ., Toronto, ON, Canada (Sedaghat, R.) || Comput. Sci. & Eng., Indian Inst. of Technol., Indore, Indore, India (Sengupta, A.) |
| Abstract | Detecting error or producing correct output is the primary function of a fault secured system. In the context of multi-cycle transient faults, design space exploration (DSE) of an optimal fault secured datapath based on user constraints of area and delay during high level synthesis (HLS) is considered notorious. This is derived from the fact that generation of a user budget bounded multi-cycle transient fault secured datapath may not be possible for every type of candidate design solution produced during exploration. Additionally, insertion of inapt cut to optimize delay overhead associated with fault security in most cases may not yield optimal solutions in the context of user constraints/budgets. This paper resolves the above problems which has not been addressed in the literature so far by proposing the following novelties: (a) fault secured particle swarm optimization (PSO) driven DSE methodology (b) Techniques to handle multi-cycle transient faults during DSE (c) Schemes for choosing pertinent edges for inserting cut (s) in scheduled Control Data Flow Graph (CDFG) that optimizes the delay overhead associated with fault security. Results of the proposed approach indicated that the fault secured solution found comprehensively minimizes the final cost as well as satisfies the conflicting user budgets. Further, the final fault secured solution yielded is significantly lower in cost compared to solutions obtained through recent similar approaches. |
| Starting Page | 69 |
| Ending Page | 74 |
| File Size | 238152 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479958276 |
| ISSN | 08407789 |
| e-ISBN | 9781479958290 |
| DOI | 10.1109/CCECE.2015.7129162 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-05-03 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Delays Hardware Transient analysis Security Circuit faults Convergence Resource management |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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