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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lan Liu Luke, D. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., New Brunswick Univ., Fredericton, NB, Canada (Lan Liu; Luke, D.) |
| Abstract | Rijndael is the new advanced encryption standard (AES) that was chosen by the American National Institute of Standards and Technology (NIST) in October 2000. This paper investigates the implementation of the 128 bits key size AES algorithm using an iterative architecture in a 0.18 micron semi-custom ASIC using a CMOS standard cell library. Our research focuses on the basic electronic codebook (ECB) mode. The circuit was efficiently designed to have both encryption and decryption functions. Depending on the input control signal, the design can work as an encryption core or a decryption core. Our result shows that, for a clock frequency of 100 MHz, we can achieve a throughput of more than 1 Gbps. The core area is approximately 2.6 mm/sup 2/. This high-speed hard macro can be used as a reusable IP block to be embedded into a system-on-chip (SOC) design in the future. |
| Starting Page | 53 |
| Ending Page | 56 |
| File Size | 287454 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780377818 |
| ISSN | 08407789 |
| DOI | 10.1109/CCECE.2003.1226342 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-05-04 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Cryptography NIST Iterative algorithms Application specific integrated circuits Libraries Signal design Clocks Frequency Throughput System-on-a-chip |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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