NDLI: A comprehensive study of three moduli sets for residue arithmetic

Content Provider	IEEE Xplore Digital Library
Author	Wei Wang Swamy, M.N.S. Ahmad, M.O. Yuke Wang
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada (Wei Wang)
Abstract	One important problem in residue arithmetic is the choice of modulo sets to represent the binary numbers in a certain range. In recent years, several general three-modulo sets have been introduced, and each of them is claimed to have some advantages. In this paper, we carry out a comprehensive study for all these modulo sets from the point of view of the hardware complexity and the speed of their residue-to-binary converters. Based on a performance evaluation of the VLSI implementation in terms of area and delay, we conclude that to represent 8-bit, 16-bit, 32-bit and 64-bit binary numbers, the set of moduli {2/sup n/-1, 2/sup n/, 2/sup n/+1} has the fastest residue-to-binary converter requiring the smallest area. The converter for this moduli set is designed based on the new Chinese remainder theorem of Y. Wang (1998).
Starting Page	513
Ending Page	518
File Size	415039
Page Count	6
File Format	PDF
ISBN	0780355792
ISSN	08407789
DOI	10.1109/CCECE.1999.807251
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-09
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital arithmetic Hardware Very large scale integration Delay Signal processing Concurrent computing Digital signal processing Application software Fast Fourier transforms Digital filters
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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