NDLI: A Method for Improving the Verification and Validation of Systems by the Combined Use of Simulation and Formal Methods

Content Provider	IEEE Xplore Digital Library
Author	Yacoub, A. Hamri, M. Frydman, C.
Copyright Year	2014
Description	Author affiliation: ENSAM, Aix Marseille Univ., Marseille, France (Yacoub, A.; Hamri, M.; Frydman, C.)
Abstract	Verification and Validation (V&V) of Systems is an important process in the development of systems, in order to ensure that they are reliable and operational. Among methods of V&V, there are two that seem to be opposite to each other: simulation, which is empirical, and formal verification, which is comprehensive. Moreover, simulation and formal verification propose many different formalisms, increasing the gap between them. But, jointly used, these two powerful tools allow making a more efficient verification, increasing the confidence we can put in the verified systems. The main problem is how we can combine their use and how we can reduce the gap created by the nature of both of them. This paper presents guidelines and a general approach in order to use simulation, and especially discrete-event simulation, on a model specified in a verifiable formal language.
Starting Page	155
Ending Page	162
File Size	309697
Page Count	8
File Format	PDF
ISBN	9781479961436
ISSN	15506525
e-ISBN	9781479961443
DOI	10.1109/DS-RT.2014.27
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-01
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automata Games Clocks Computational modeling Couplings Complexity theory Mathematical model Transformation Formal Methods Spin PROMELA Formal Verification DEVS FDDEVS Simulation
Content Type	Text
Resource Type	Article

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A Method for Improving the Verification and Validation of Systems by the Combined Use of Simulation and Formal Methods

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