NDLI: Safety of Deferred Update in Transactional Memory

Content Provider	IEEE Xplore Digital Library
Author	Attiya, H. Hans, S. Kuznetsov, P. Ravi, S.
Copyright Year	2013
Abstract	Transactional memory allows the user to declare sequences of instructions as speculative transactions that can either commit or abort. If a transaction commits, it appears to be executed sequentially, so that the committed transactions constitute a correct sequential execution. If a transaction aborts, none of its instructions can affect other transactions. The popular criterion of opacity requires that the views of aborted transactions must also be consistent with the global sequential order constituted by committed ones. This is believed to be important, since inconsistencies observed by an aborted transaction may cause a fatal irrecoverable error or waste of the system in an infinite loop. Intuitively, an opaque implementation must ensure that no intermediate view a transaction obtains before it commits or aborts can be affected by a transaction that has not started committing yet, so called deferred-update semantics. In this paper, we intend to grasp this intuition formally. We propose a variant of opacity that explicitly requires the sequential order to respect the deferred-update semantics. Unlike opacity, our property also ensures that a serialization of a history implies serializations of its prefixes. Finally, we show that our property is equivalent to opacity if we assume that no two transactions commit identical values on the same variable, and present a counter-example for scenarios when the “unique-write” assumption does not hold.
Starting Page	601
Ending Page	610
File Size	459399
Page Count	10
File Format	PDF
ISBN	9780769550008
ISSN	10636927
DOI	10.1109/ICDCS.2013.57
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	History Silicon Law Real-time systems Safety Semantics Limit-closure Transactional Memory
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Make the Leader Work: Executive Deferred Update Replication

Hybrid Replication: State-Machine-Based and Deferred-Update Replication Schemes Combined

RAM-DUR: In-Memory Deferred Update Replication

SPECULA: Speculative Replication of Software Transactional Memory

Scoped types for real-time Java

The design of large real-time systems: the time-triggered approach

STMBench7:a benchmark for software transactional memory

STMBench7: a benchmark for software transactional memory

WCET analysis of probabilistic hard real-time systems

Safety of Deferred Update in Transactional Memory

Similar Documents

Make the Leader Work: Executive Deferred Update Replication

Hybrid Replication: State-Machine-Based and Deferred-Update Replication Schemes Combined

RAM-DUR: In-Memory Deferred Update Replication

SPECULA: Speculative Replication of Software Transactional Memory

Scoped types for real-time Java

The design of large real-time systems: the time-triggered approach

STMBench7:a benchmark for software transactional memory

STMBench7: a benchmark for software transactional memory

WCET analysis of probabilistic hard real-time systems

Safety of Deferred Update in Transactional Memory