NDLI: Design and fabrication of a tri-C30 multichip module building block

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Design and fabrication of a tri-C30 multichip module building block

Content Provider	IEEE Xplore Digital Library
Author	Staggs, J. Smith, J.
Copyright Year	1997
Description	Author affiliation: Nichols Fed., USA (Staggs, J.)
Abstract	A real-time architecture was designed, developed and fabricated that targets an application through the MiP (Monolithic Interceptor Processor) program. This MCM, as an elemental building block for parallel real-time DSP applications was designed and built in the standard MiP size and format. This PDA (Parallel Digital signal processing Array) is capable of 400 MFLOPS (at 33 MHz) within a volume of 2 in/sup 3/. Due to the minimized circuit parasitics of HDI packaging, much higher clock speed, hence MFLOPS, are quite likely. Though the evaluation of the PDA was not completed, the MiP project developed what could be the smallest and most capable real-time PDA to date. In order to support intermediate testing, a key "known good module" test fixture was also developed. It then provided for the demonstration of key design and methodologies that continue to be used.
File Size	566859
File Format	PDF
ISBN	0780341503
DOI	10.1109/DASC.1997.635028
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Multichip modules Electronics packaging Integrated circuit interconnections Throughput Signal design Signal processing Digital signal processing Image processing Substrates
Content Type	Text
Resource Type	Article

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