NDLI: Tracking-Vgs: A Temperature Compensation Technique to Implement all-MOS Reference Voltages

Content Provider	IEEE Xplore Digital Library
Author	Cajueiro, J.P.C. dos Reis Filho, C.A.
Copyright Year	2006
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Campinas State Univ. (Cajueiro, J.P.C.; dos Reis Filho, C.A.)
Abstract	A novel temperature compensation technique to implement reference voltages in CMOS circuits is described, starting from the theoretical basis up to results obtained from experimental verification of a test circuit. The proposed technique is based on the fact that, since the V $_{GS}$ voltage of a MOS transistor can either increase or decrease with increasing temperature depending on the operating channel current $I_{D},$ a voltage with amplitude $nV_{GS}$ produced by a stack of n transistors can feature the same rate of change with the temperature as the $V_{GS}$ of a single transistor, provided the single transistor and the stack of n transistors are biased each with the appropriate channel currents. In such conditions, the difference between the two voltages is constant. An alternative to produce the mentioned $nV_{GS}$ voltage, instead of a stack of n transistors, is a floating gate transistor, whose equivalent $V_{GS}$ voltage can be adjusted by depositing charges in its floating gate. This is actually the preferred implementation of the proposed technique cause it adds the benefit of adjusting infield the amplitude of the reference voltage. Samples of a test circuit were fabricated in 0.35mum CMOS aiming at to validate the technique. Results have confirmed what was expected from the proposed technique: Measured from - 40 to 120degC the circuits have shown a temperature coefficient of circa 100ppm/%deg;C. While the insensitivity to the temperature obtained from the implemented reference voltage has not exceeded the current state of the art, which is about 1ppm/degC, the proposed technique contributes to the implementation of reference voltages that use only MOS transistors and that feature in-field adjustment
Starting Page	287
Ending Page	291
File Size	4680311
Page Count	5
File Format	PDF
ISBN	1424400414
DOI	10.1109/ICCDCS.2006.250875
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-26
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Circuit testing Temperature dependence Photonic band gap CMOS technology Current density Threshold voltage Circuits and systems System testing Bipolar transistors
Content Type	Text
Resource Type	Article

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