NDLI: 35 nm-Lg raised S/D In0.53Ga0.47As quantum-well MOSFETs with 81 mV/decade subthreshold swing at VDS=0.5 V

Content Provider	IEEE Xplore Digital Library
Author	Sanghoon Lee Cheng-Ying Huang Elias, D.C. Thibeault, B.J. Mitchell, W. Chobpattana, V. Stemmer, S. Gossard, A.C. Rodwell, M.J.W.
Copyright Year	2014
Description	Author affiliation: ECE Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Sanghoon Lee; Cheng-Ying Huang; Elias, D.C.; Thibeault, B.J.; Mitchell, W.; Rodwell, M.J.W.) \|\| Mater. Dept., Univ. of California, Santa Barbara, Santa Barbara, CA, USA (Chobpattana, V.; Stemmer, S.; Gossard, A.C.)
Abstract	Recently, InAs or In-rich InGaAs (In>53%) has been widely studied as the channel material for III-V FETs due to its superior electron transport properties over $In_{0.53}Ga_{0.47}As.$ These materials provide excellent on-state characteristics, e.g. >2.5 mS/μm peak transconductanc $(g_{m})$ at $V_{DS}=0.5$ V [1-3]. The narrow bandgap in these materials, however, causes band-to-band tunneling (BTBT) in the high drain-field region even at relatively low supply voltage of 0.5 V, thus resulting in high leakage at the off-state [1][3]. In our previous work, in order to address this issue, we incorporated a vertical spacer between the channel and N+ source/drain (S/D) to accommodate the depletion region near the channel-drain junction. The spacer significantly improved off-state characteristics such as off-state leakage, drain-induced barrier lowering (DIBL), and subthreshold swing (SS) without increasing the device footprint [3], [4]. In this work, by adopting a ~4 nm-thick $In_{0.53}Ga_{0.47}As$ channel instead of a thick InAs channel, we have further improved the off-state characteristics at high $V_{DS}$ and achieved 81 mV/dec. minimum subthreshold swing $(SS_{min})$ for a 35 $nm-L_{g}$ device at $V_{DS}=0.5$ V and 385 μA/μm on-current $(I_{on})$ at 100 nA/μm off-current $(I_{off})$ and $V_{DD}=0.5$ V, which are the best $SS_{min}$ and $I_{on}$ from all reported $In_{0.53}Ga_{0.47}As$ channel FETs.
Starting Page	223
Ending Page	224
File Size	299489
Page Count	2
File Format	PDF
ISBN	9781479954056
e-ISBN	9781479954063
DOI	10.1109/DRC.2014.6872378
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates MOSFET Gold Indium gallium arsenide Hafnium compounds
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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