NDLI: RF performance of 3D III-V nanowire T-Gate HEMTs grown by VLS method

Content Provider	IEEE Xplore Digital Library
Author	Chabak, K.D. Xin Miao Chen Zhang Walker, D.E. Xiuling Li
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Chabak, K.D.; Xin Miao; Chen Zhang; Xiuling Li) \|\| Sensors Directorate, Air Force Res. Lab., Wright-Patterson AFB, OH, USA (Walker, D.E.)
Abstract	Continued down-scaling of digital and RF electronics has spawn new research efforts in various nanotechnologies such as 2D semiconducting sheets and nanowires as the conducting transistor channel. Nanoscale field-effect transistors (FETs) promise to bring power-efficient operation, improved short channel effects, and added functionalities beyond conventional top-down planar devices such as facile heterogeneous integration. So far, impressive results with $f_{T}$ > 400 GHz have been achieved with graphene FETs [1]. However, the highest achieved $f_{max}$ for carbon-based devices is below 70 GHz [2] which is related to poor output conductance $(g_{ds})$ and weak channel modulation either from metallic carbon nanotubes or a metallic-like gapless graphene channel. While a high $f_{T}$ is important, FETs generally benefit from $f_{max}$ > $f_{T}$ for amplification of RF signals [3]. III-V nanowires (NWs), on the other hand, retain well-known transport characteristics with inherent 3D profile for improved electrostatics. The most commonly used growth method for NWs is via the metal-assisted vapor-liquid-solid (VLS) mechanism. Several III-V NW FETs have been reported with excellent dc performance, but preference for NW growth to proceed normal to the substrate has stunted RF devices where arrays of NW channels are required to deliver sufficiently high raw current. Vertical InAs NW FETs have been reported with impressive 100+ GHz performance, but remain limited by challenging device fabrication and parasitic overlapping pad capacitance [4,5]. Both of these limitations can be avoided by growing high-density NW arrays along the surface of the substrate. Here, we present the first demonstration of VLS grown III-V NW channels self-assembled in parallel arrays with $f_{T}/f_{max}$ > 30/70+ GHz using a GaAs channel. These results are state-of-the-art for III-V NWs assembled in planar arrays.
Starting Page	211
Ending Page	212
File Size	416792
Page Count	2
File Format	PDF
ISBN	9781479954056
e-ISBN	9781479954063
DOI	10.1109/DRC.2014.6872372
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electron devices Reliability Nanoscale devices Decision support systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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