NDLI: Multi-layer MoTe2 p-channel MOSFETs with high drive current

Content Provider	IEEE Xplore Digital Library
Author	Haratipour, N. Koester, S.J.
Copyright Year	2014
Description	Author affiliation: ECE Dept., Univ. of Minnesota-Twin Cities, Minneapolis, MN, USA (Haratipour, N.; Koester, S.J.)
Abstract	Transition metal dichalcogenides (TMDs) are interesting materials for electronic applications due to their layered crystal structure, which offers the potential to realize transistors with ultra-thin or even monolayer body thicknesses [1]. Unlike single-layer graphene, TMDs typically have band gaps in the range of 1-2 eV, making them suitable for logic transistor applications [2]. $MoTe_{2}$ is an ideal material for p-MOSFETs due to its low electron affinity and relatively narrow band gap of ~ 1 eV [3]. $MoTe_{2}$ is also of interest for realizing tunneling field effect transistors (TFETs) with highly-staggered or broken-gap band alignments [4], particularly when integrated with high electron affinity TMDs, such as $SnSe_{2}$ [5]. However, to date, only n-MOSFETs and ambipolar transistors have been demonstrated experimentally using thin-film $MoTe_{2}$ [6, 7]. In this work, we report the characteristics of p-MOSFETs using exfoliated $MoTe_{2}$ with Pd contact metallization. We characterize the properties of these backgated devices as a function of temperature and extract the Schottky barrier height of the Pd metallization. We also show that strong p-type doping occurs in these devices after prolonged exposure to ambient atmosphere, resulting in p-MOSFETs with linear contacts and drive current approaching 100 uA/um.
Starting Page	171
Ending Page	172
File Size	701337
Page Count	2
File Format	PDF
ISBN	9781479954056
e-ISBN	9781479954063
DOI	10.1109/DRC.2014.6872352
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Logic gates Atmosphere MOSFET Schottky barriers Materials
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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