NDLI: A surface-potential based compact model for GaN HEMTs incorporating polarization charges

Content Provider	IEEE Xplore Digital Library
Author	Jana, R. Jena, D.
Copyright Year	2012
Description	Author affiliation: Electrical Engineering, University of Notre Dame, IN 46556, USA (Jana, R.; Jena, D.)
Abstract	High electron mobility transistors (HEMTs) based on III-nitride semiconductor heterostructures are being actively pursued for high-voltage and high-speed microwave applications [1]. As discrete GaN transistors move towards integration in circuits, a compact model for device operation is highly desirable to aid systematic design. GaN HEMTs differ from Silicon and other III-V FETs through the presence of high density polarization-induced sheet charges at heterostructure interfaces. Till date, no clear method exists to incorporate such polarization charges into compact modeling of HEMTs. We introduce a method for incorporating polarization sheet charges into compact modeling in transistors. The Poisson equation is solved directly with a Dirac-delta function sheet charge at the heterojunction to obtain an analytical equation for the surface potential. This surface potential is then used to calculate the HEMT characteristics. Thus, the results of this work for the first time make an explicit connection between the material properties of the HEMT heterostructure with a surface potential based compact model through the polarization sheet charge. Furthermore, we have extended the intrinsic model by including field-dependent mobility and velocity saturation. The developed model should prove helpful in designing of devices and circuits.
Starting Page	147
Ending Page	148
File Size	469343
Page Count	2
File Format	PDF
ISBN	9781467311632
ISSN	15483770
e-ISBN	9781467311649
DOI	10.1109/DRC.2012.6257018
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	HEMTs MODFETs Gallium nitride Logic gates Electric potential Heterojunctions Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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