NDLI: Steep subthreshold slope nanowire FETs with gate-induced Schottky-barrier tunneling

Content Provider	IEEE Xplore Digital Library
Author	Qiliang Li Xiaoxiao Zhu Ioannou, D. Suehle, J. Richter, C.
Copyright Year	2009
Description	Author affiliation: Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD 20899 (Suehle, J.; Richter, C.) \|\| Dept. of Electrical and Computer Engineering, George Mason University, Fairfax, VA 22030 (Qiliang Li; Xiaoxiao Zhu; Ioannou, D.)
Abstract	We report Schottky-barrier (S-B) nanowire field effect transistors (NW FETs) with high-performance characteristics brought about by gate-induced Schottky-barrier tunneling. The devices exhibit sharp subthreshold slopes (as small as 45 mV/dec), well-saturated inversion-mode IDS−VDS characteristics, and large on/off current ratios (≈ $10^{8}).$ The excellent device properties are attributed to: (i) the enhancement of tunneling through the NW FET S-B by the gate-channel-source coupling which results in sharp subthreshold slope, (ii) the clean, CMOS-compatible fabrication of NW FET leading to a high-quality dielectric/nanowire interface, and (iii) the good quality S/D barriers and low S/D series resistance associated with them. Previous studies have demonstrated high-performance nanowire and nanotube FETs with on/off current ratios ≈ $10^{5}$ and subthreshold swings (SS's) ≈ 100 mV/dec [1, 2]. The sharpness of the SS is a critical parameter in determining how small a fraction of the applied gate voltage is used to switch the device on and thus the maximum dissipated power. Previous pioneering results [3–5] have shown that nanotube and nanowire FETs with SS < 60 mV/dec can be achieved based on avalanche breakdown or interband tunneling in the un-gated channel regions between the gate and S/D. Typically such devices require large drain voltages and may have large series resistance, non-saturating IDS-VDS, small on/off ratios and ambipolar conduction. The S-B NW FETs fabricated in this work exhibit sharp SS's at low operation voltage, large on/off current ratios and inversion-mode saturating IDS-VDS.
Starting Page	113
Ending Page	114
File Size	987546
Page Count	2
File Format	PDF
ISBN	9781424435289
ISSN	15483770
DOI	10.1109/DRC.2009.5354865
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FETs Tunneling Nanoscale devices Intrusion detection Delay Switches Low voltage MOSFETs NIST Fabrication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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