NDLI: Mixed mode double-gate FET model

Content Provider	IEEE Xplore Digital Library
Author	Solomon, R.M.
Copyright Year	2001
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Solomon, R.M.)
Abstract	A general purpose double-gate FET (DGFET) model is presented which is capable of handling a wide variety of DGFET configurations and arbitrary potentials on its four terminals. The heart of the model is the mixed-mode algorithm which, under appropriate bias conditions, transforms the DGFET into two single gate FETs (SGFET) in series. The single gate FET model itself uses a new treatment of the space charge region, allowing the DGFET to be realistically simulated well into the punch-through regime. Sub-threshold and short-channel effects are included and an effective perpendicular electric field, modified by the short-channel charge, is derived for the DGFET and used in mobility calculations. Additional mobility terms can be added to account for scattering at either interface. In addition to currents, voltage dependent capacitances are also derived, including sub-threshold gate to gate capacitances, enabling realistic simulations of coupled circuit noise to be undertaken.
Sponsorship	Electron Devices Soc
Starting Page	77
Ending Page	78
File Size	169211
Page Count	2
File Format	PDF
ISBN	0780370147
DOI	10.1109/DRC.2001.937880
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Double-gate FETs Circuit simulation Electrons Threshold voltage Capacitance Semiconductor device modeling Silicon Voltage control Heart Space charge
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

Mathematical Modelling for Double-Gate MOSFETs

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

Unified regional modeling approach to emerging multiple-gate/nanowire MOSFETs

Mobility in Back-Gate/Double-Gate Undoped Thin Silicon Channel Transistors

A simple equation model for RF MOS FET

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

Threshold voltage model of deep submicrometer double-gate fully-depleted SOI MOS devices

Implementation and validation of a new diode model for circuit simulation

Mixed mode double-gate FET model

Similar Documents

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

Mathematical Modelling for Double-Gate MOSFETs

BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design

Unified regional modeling approach to emerging multiple-gate/nanowire MOSFETs

Mobility in Back-Gate/Double-Gate Undoped Thin Silicon Channel Transistors

A simple equation model for RF MOS FET

A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure

Threshold voltage model of deep submicrometer double-gate fully-depleted SOI MOS devices

Implementation and validation of a new diode model for circuit simulation

Mixed mode double-gate FET model