NDLI: A sub 40-nm body thickness n-type FinFET

Content Provider	IEEE Xplore Digital Library
Author	Fried, D.M. Johnson, A.P. Nowak, E.J. Rankin, J.H. Willets, C.R.
Copyright Year	2001
Description	Author affiliation: IBM Microelectron. Div., Essex Junction, VT, USA (Fried, D.M.)
Abstract	We experimentally demonstrate near-ideal subthreshold behavior of fully-depleted fin-style double-gate n-type MOSFETs and the best measured transconductance Gm-sat = 72 S/m (>400 S/m intrinsic) for sub-40 nm n-type FinFETs reported. This silicon nFET exhibits experimental ideality n = 1.13, in good agreement with the deviation from unity expected due only to source/drain coupling. These results comprise the best behavior for 100 nm-scale double-gate nFETs in terms of channel subthreshold characteristics and gate leakage observed experimentally to date. Hisamoto et al. (1989) introduced experimental results on doubld-gate silicon MOSFETs in which the channel is formed by etching single-crystal silicon to leave a vertical fin standing, forming a gate which wraps around the fin, with source and drain regions on the two ends of the fin. This basic idea was further refined to sub-50 nm n-type MOSFETs and then extended to sub-50 nm p-type MOSFETs. Using simplified fabrication techniques, we demonstrate improved behavior, from an intrinsic channel point of view, of the nFET work, using conventional CMOS integration on n-type FinFETs.
Sponsorship	Electron Devices Soc
Starting Page	24
Ending Page	25
File Size	211953
Page Count	2
File Format	PDF
ISBN	0780370147
DOI	10.1109/DRC.2001.937857
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Silicon MOSFETs Gate leakage Etching Oxidation Electrodes Lithography Implants Voltage
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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