NDLI: Architectures for efficient face authentication in embedded systems

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Architectures for efficient face authentication in embedded systems

Software implementation of Tate pairing over GF(2/sup m/)

Optimization of Regular Expression Pattern Matching Circuits on FPGA

Satisfiability-based Framework for Enabling Side-channel Attacks on Cryptographic Software

An 830mW, 586kbps 1024-bit RSA chip design

Platform Independent Debug Port Controller Architecture with Security Protection for Multi-Processor System-on-Chip ICs

Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time

Energy-Efficient FPGA Interconnect Design

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Application specific instruction processor based implementation of a GNSS receiver on an FPGA

A Methodology for FPGA to Structured-ASIC Synthesis and Verification

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A practical implementation of the fault-tolerant Daisy-chain clock synchronization algorithm on CAN

On the verification of automotive protocols

FlexRay Transceiver in a 0.35µm CMOS High-Voltage Technology

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Mixed-Signal Design of a Digital Input Power Amplifier for Automotive Audio Applications

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Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit

A Novel FPGA-based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation

ASIP Design and Synthesis for Non Linear Filtering in Image Processing

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The Vector Fixed Point Unit of the Synergistic Processor Element of the Cell Architecture Processor

Design and Test of Fixed-point Multimedia Co-processor for Mobile Applications

Volume 1 - 2006

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Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition

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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

Proceedings Design, Automation and Test in Europe

Architectures for efficient face authentication in embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Aaraj, N. Ravi, S. Raghunathan, S. Jha, N.K.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ (Aaraj, N.)
Abstract	Biometrics represents a promising approach for reliable and secure user authentication. However, they have not yet been widely adopted in embedded systems, particularly in resource-constrained devices such as cell phones and personal digital assistants (PDAs). In this paper, we investigate the challenges involved in using face-based biometrics for authenticating a user to an embedded system. To enable high authentication accuracy, we consider robust face verifiers based on principal component analysis/linear discriminant analysis (PCA-LDA) algorithms and Bayesian classifiers, and their combined use (multi-modal biometrics). Since embedded systems are severely constrained in their processing capabilities, algorithms that provide sufficient accuracy tend to be computationally expensive, leading to unacceptable authentication times. On the other hand, achieving acceptable performance often comes at the cost of degradation in the quality of results. Our work aims at developing embedded processing architectures that improve face verification speed with minimal hardware requirements and without any compromise in verification accuracy. We analyze the computational characteristics of face verifiers when running on an embedded processor, and systematically identify opportunities for accelerating their execution. We then present a range of targeted hardware and software enhancements that include the use of fixed-point arithmetic, various code optimizations, application-specific custom instructions and co-processors, and parallel processing capabilities in multi-processor systems-on-chip (SoCs). We evaluated the proposed architectures in the context of open-source face verification algorithms running on a commercial embedded processor (Xtensa from Tensilica). Our work shows that fast, in-system verification is possible even in the context of many resource-constrained embedded systems. We also demonstrate that high authentication accuracy can be achieved with minimum hardware overheads, while requiring no modifications to the core face verification algorithms
File Size	1579268
File Format	PDF
ISBN	3981080114
DOI	10.1109/DATE.2006.244155
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-06
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	European Design Automation Association (EDAA)
Subject Keyword	Authentication Embedded system Biometrics Hardware Personal digital assistants Embedded computing Computer architecture Open source software Cellular phones Robustness
Content Type	Text
Resource Type	Article

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