NDLI: A method of delay fault test generation

Content Provider	IEEE Xplore Digital Library
Author	Glover, C.T. Mercer, M.R.
Copyright Year	1988
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Austin Univ., TX, USA (Glover, C.T.; Mercer, M.R.)
Abstract	The authors propose an efficient deterministic method of delay fault test generation. For most common circuits, the proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. They define a type of transition path, the fully transitional path (FTP), and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input. The authors extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at-tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that the method provides a higher robust delay fault coverage than pseudorandom patterns at less than one-fifth the cost.<>
Starting Page	90
Ending Page	95
File Size	588427
Page Count	6
File Format	PDF
ISBN	0818608641
ISSN	0738100X
DOI	10.1109/DAC.1988.14740
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-06-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit testing Costs Latches Combinational circuits Propagation delay Fault detection Computational modeling Circuit simulation Computer simulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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