NDLI: Electrical Optimization of PLAs

Content Provider	IEEE Xplore Digital Library
Author	Hedlund, K.S.
Copyright Year	1985
Description	Author affiliation: Department of Computer Science, University of North Carolina, Chapel Hill, NC (Hedlund, K.S.)
Abstract	This work addresses the problem of improving an nMOS PLA's speed and power consumption through modifications to the transistor sizes in the PLA. A simplified model of gate delay (lumped RC model) is used that allows rapid estimation of delays thus allowing interactive computation of optimal transistor sizes. Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay. Both these minima are computed subject to bounds on the transistor sizes. A prototype electrical optimization tool was compared to the PLA generation tools in the Berkeley CAD tools package (eqntott and tpla). The maximum delay through a PLA can often be reduced by a factor of 2, and power consumption along the critical paths can be reduced by 10 - 30% without increasing maximum delay.
Starting Page	681
Ending Page	687
File Size	721447
Page Count	7
File Format	PDF
ISBN	0818606355
ISSN	0738100X
DOI	10.1109/DAC.1985.1586016
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1985-06-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programmable logic arrays Energy consumption Design optimization Delay estimation MOS devices Prototypes Topology Circuits Computer science Minimization methods
Content Type	Text
Resource Type	Article

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