NDLI: Performance-driven multi-level clustering with application to hierarchical FPGA mapping

Content Provider	IEEE Xplore Digital Library
Author	Cong, J. Romesis, M.
Copyright Year	2001
Description	Author affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA (Cong, J.)
Abstract	In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven multi-level clustering problem is NP-hard (in contrast to the fact that single-level performance-driven clustering can be solved in polynomial time optimally). Then, we present an efficient heuristic for two-level clustering for delay minimization. It can also provide area-delay trade-off by controlling the amount of node duplication. The algorithm is applied to Altera's latest APEX FPGA architecture which has a two-level hierarchy. Experimental results with combinational circuits show that with our performance-driven two-level clustering solution we can improve the circuit performance produced by the Quartus Design System from Altera by an average of 15% for APEX devices measured in terms of delay after final layout. To our knowledge this is the first in-depth study for the performance-driven multi-level circuit clustering problem.
Starting Page	389
Ending Page	394
File Size	600526
Page Count	6
File Format	PDF
ISBN	1581132972
ISSN	0738100X
DOI	10.1109/DAC.2001.156171
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Field programmable gate arrays Delay Integrated circuit interconnections Clustering algorithms Minimization Application software Logic arrays Computer science Polynomials Permission
Content Type	Text
Resource Type	Article

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