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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cabodi, G. Camurati, P. Qner, S. |
| Copyright Year | 1999 |
| Description | Author affiliation: Dipt. di Autom. e Inf., Politecnico di Torino, Italy (Cabodi, G.) |
| Abstract | Symbolic techniques have undergone major improvements in the last few years. Nevertheless they are still limited by the size of the involved BDDs, and extending their applicability to larger and real circuits is a key issue. Within, this framework, we introduce "activity profiles" as a novel technique to characterize transition relations. In our methodology a learning phase is used to collect activity measures, related to time and space cost, for each BDD node of the transition relation. We use inexpensive reachability analysis as learning technique, and we operate within inner steps of image computations involving the transition relation and state sets. The above informations can be used for several purposes. In particular, we present an application of activity profiles in the field of reachability analysis itself. We propose transition relation subsetting and partial traversals of the state transition graph. We show that a sequence of partial traversals is able to complete a reachability analysis problem with smaller memory requirement and improved time performance. |
| Starting Page | 306 |
| Ending Page | 311 |
| File Size | 597590 |
| Page Count | 6 |
| File Format | |
| ISBN | 1581130929 |
| DOI | 10.1109/DAC.1999.781331 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-06-21 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Association for Computing Machinery, Inc. (ACM) |
| Subject Keyword | Reachability analysis Data structures Boolean functions Circuits Binary decision diagrams Costs Formal verification Explosions Hardware Permission |
| Content Type | Text |
| Resource Type | Article |
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