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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tojo, N. Togawa, N. Yanagisawa, M. Ohtsuki, T. |
| Copyright Year | 2009 |
| Description | Author affiliation: Dept. of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, 169-8555 Japan (Tojo, N.; Togawa, N.; Yanagisawa, M.; Ohtsuki, T.) |
| Abstract | In recent years, the gap between the cycle time of processors and memory access time has been increasing. One of the solutions to solve this problem is to use a cache. But just using a large cache may not reduce the total memory access time. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: a cache set size, a line size, and an associativity. In this paper, we propose two exact cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but increase simulation speed dramatically. By using our approach, the number of cache hit/miss judgments required for simulating all the cache configurations is reduced to 31.4%-93.6% compared to conventional approaches. As a result, our proposed approach totally runs an average of 1.8 times faster and a maximum of 3.3 times faster compared to the fastest approach proposed so far. Our proposed exact cache simulation approach achieves the world fastest L1 cache simulation. |
| Starting Page | 817 |
| Ending Page | 822 |
| File Size | 245680 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424427482 |
| DOI | 10.1109/ASPDAC.2009.4796581 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-01-19 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Embedded system Analytical models Computational modeling Computer simulation Computer science |
| Content Type | Text |
| Resource Type | Article |
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