NDLI: Efficient custom instruction generation based on characterizing of basic blocks

Content Provider	IEEE Xplore Digital Library
Author	Guoqiang Liang Yuchun Ma Kang Zhao Jinian Bian
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Guoqiang Liang; Yuchun Ma; Kang Zhao; Jinian Bian)
Abstract	The application specific instruction-set processor (ASIP) offers better computing performance and efficiency by exploiting a set of specific custom instructions (CI) in the processor. However, traditional approaches suffer from the problem that it costs so much computational resource to enumerate and select the optimal custom instructions. In this paper, instead of generating the custom instructions by enumerating all sub-graphs in the data flow graph, we propose a novel custom instruction generation algorithm based on analyzing the basic blocks (BB) which are the smallest execution units of the program. On the basis of characterizing the logic information and structure of basic blocks, both the identification and selection processes could be more efficient by focusing on the feasible candidates with better benefits. A Maximal Weight Independent Set-based formulation is set up to select the final custom instructions based on the efficient identification of candidate custom instructions with logic information of BBs. The experimental result shows that our algorithm can identify 55% more feasible CIs compared with the previous approach. With efficient identification process, we can finally get better CI designs with about 3.27X performance gain of the whole system.
Starting Page	98
Ending Page	103
File Size	492886
Page Count	6
File Format	PDF
ISBN	9781467360845
e-ISBN	9781467360852
DOI	10.1109/CSCWD.2013.6580946
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-27
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance gain Hardware Partitioning algorithms Benchmark testing Algorithm design and analysis Runtime Ports (Computers) basic block reconfigurable processors custom insturction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic custom instruction identification in memory streaming algorithms

Efficient custom instructions generation for system-level design

Efficient custom instruction enumeration for extensible processors

Efficient maximal convex custom instruction enumeration for extensible processors

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

Efficient management of custom instructions for run-time reconfigurable instruction set processors

An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Characterizing and improving the performance of Intel Threading Building Blocks

Efficient custom instruction generation based on characterizing of basic blocks

Similar Documents

Automatic custom instruction identification in memory streaming algorithms

Efficient custom instructions generation for system-level design

Efficient custom instruction enumeration for extensible processors

Efficient maximal convex custom instruction enumeration for extensible processors

Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration

Efficient management of custom instructions for run-time reconfigurable instruction set processors

An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Characterizing and improving the performance of Intel Threading Building Blocks

Efficient custom instruction generation based on characterizing of basic blocks