NDLI: Automated formal approach for debugging dividers using dynamic specification

Content Provider	IEEE Xplore Digital Library
Author	Haghbayan, M.-H. Alizadeh, B. Rahmani, A.-M. Liljeberg, P. Tenhunen, H.
Copyright Year	2014
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran (Alizadeh, B.) \|\| Dept. of Inf. Technol., Univ. of Turku, Turku, Finland (Haghbayan, M.-H.; Rahmani, A.-M.; Liljeberg, P.; Tenhunen, H.)
Abstract	This paper presents a formal approach to verify and debug division circuits. The proposed technique is based on a reverse-engineering mechanism where a high-level model of the gate-level implementation is obtained and then an intermediate representation of the specification is introduced. This process makes equivalence checking between two models possible. The main advantage of this representation is the fact that the specification is dynamically changed according to the information obtained from the implementation. At the end, if two updated models are not equivalent, possible bugs can be localized and then corrected automatically by analyzing the difference. Experimental results show the robustness of the proposed approach in comparison with other contemporary methods in terms of the run time execution. The results also reveal that up to two orders of magnitude of average speedup can be obtained compared with the state-of-the-art.
Starting Page	264
Ending Page	269
File Size	369261
Page Count	6
File Format	PDF
e-ISBN	9781479961559
DOI	10.1109/DFT.2014.6962068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-01
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Fault tolerant systems Very large scale integration Nanotechnology Discrete Fourier transforms Formal models Arithmetic and logic units Debugging aids Diagnostics Verification
Content Type	Text
Resource Type	Article

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