NDLI: A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems

Content Provider	IEEE Xplore Digital Library
Author	Bolchini, C. Castro, F. Miele, A.
Copyright Year	2009
Abstract	This paper presents a new framework for the analysis of SRAM-based FPGA systems with respect to their dependability properties against single, multiple and cumulative upsets errors. The aim is to offer an environment for performing fault classification and error propagation analyses for designed featuring fault detection or tolerance techniques against soft errors, where the focus is not only the overall achieved fault coverage, but an understanding of the fault/error relation inside the internal elements of the system. We propose a fault analyzer/classifier laying on top of a classical fault injection engine, used to monitor the evolution of the system after a fault as occurred, with respect to the applied reliability-oriented design technique. The paper introduces the framework and reports some experimental results of its application to a case study, to highlight the benefits of the proposed solution.
Starting Page	173
Ending Page	181
File Size	312942
Page Count	9
File Format	PDF
ISBN	9780769538396
ISSN	15505774
DOI	10.1109/DFT.2009.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Performance analysis Error analysis Fault detection Engines Monitoring Statistical analysis Fault tolerant systems Very large scale integration Paper technology Fault Analysis Fault Injection FPGA
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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