NDLI: Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

Content Provider	IEEE Xplore Digital Library
Author	Argyrides, C. Zarandi, H.R. Pradhan, D.K.
Copyright Year	2007
Description	Author affiliation: Univ. of Bristol, Bristol (Argyrides, C.)
Abstract	This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these methods in terms of fault detection and correction of multiple faults regarding to the area overhead.
Starting Page	340
Ending Page	348
File Size	525959
Page Count	9
File Format	PDF
ISBN	9780769528854
ISSN	15505774
DOI	10.1109/DFT.2007.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Protection Fault detection Circuit faults Costs Equations Integrated circuit technology Integrated circuit noise Neutrons Single event upset
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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