NDLI: Test pattern decompression using a scan chain

Content Provider	IEEE Xplore Digital Library
Author	Novak, O. Nosek, J.
Copyright Year	2001
Description	Author affiliation: Tech. Univ. Liberec, Czech Republic (Novak, O.)
Abstract	Proposes a method of test pattern compression, which can be used for reducing the memory requirements for storing test patterns. The patterns are decompressed during testing in the scan chain. The test-per-clock testing scheme consists of a scan chain, auxiliary outputs for capturing the signals on the internal CUT outputs and a CUT test response compactor. The test-per-scan testing scheme can be used without auxiliary outputs and output compacting scheme. The algorithm of finding the compressed scan chain sequence reorders and overlaps the patterns previously generated with the help of an ATPG. These test patterns are generated in such a way that they contain maximum number of don't care bits. The scan chain sequence can be used for exercising all considered faults from the fault list of the tested circuit. Several experiments were done with ISCAS 85 and 89 benchmark circuits. Compared with other methods the proposed method substantially reduces the number of stored bits, test application time and necessary hardware overhead.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Fault-Tolerant Comput.
Starting Page	110
Ending Page	115
File Size	161756
Page Count	6
File Format	PDF
ISBN	0769512038
ISSN	15505774
DOI	10.1109/DFTVS.2001.966759
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Test pattern generators Clocks Circuit faults Logic testing Automatic test pattern generation Hardware Performance evaluation Very large scale integration Energy consumption
Content Type	Text
Resource Type	Article

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