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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Takala, J.H. Jarvinen, T.S. Salmela, P.V. Akopian, D.A. |
| Copyright Year | 2001 |
| Description | Author affiliation: Digital & Comput. Syst. Lab., Tampere Univ., Finland (Takala, J.H.) |
| Abstract | In array processors, complex data reordering is often needed to realize the interconnection topologies between the computational nodes in algorithms. Several important algorithms, e.g., discrete trigonometric transforms and Viterbi decoding, can be represented in a radix-R form where the principal topology is stride by R permutation. A general factorialization of stride permutations is derived, which can be mapped onto register-based structures for constructing area-efficient multi-port interconnection networks. The networks can be modified to support several stride permutations and sequence sizes. |
| Sponsorship | IEEE Signal Process. Soc |
| Starting Page | 1177 |
| Ending Page | 1180 |
| File Size | 421709 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780370414 |
| ISSN | 15206149 |
| DOI | 10.1109/ICASSP.2001.941133 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-05-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Multiprocessor interconnection networks Signal processing algorithms Topology Discrete transforms Read-write memory Viterbi algorithm Decoding Computer architecture Switches Laboratories |
| Content Type | Text |
| Resource Type | Article |
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