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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Radhakrishnan, D. |
| Copyright Year | 2000 |
| Description | Author affiliation: Div. of Comput. Eng., Nanyang Technol. Inst., Singapore (Radhakrishnan, D.) |
| Abstract | There is a tremendous need for miniaturization as well as low power consumption in many signal-processing systems, especially when they are used in portable equipment. In this context, the design of low power DSP processors receives utmost importance. A clever means of achieving this is by use of pass logic circuits in these designs. But switching activity is found to be a major contributor in dynamic power consumption. Hence, a formal technique for calculating the switching activity in CMOS pass networks is presented in this paper, which is validated using various designs of CMOS full adder cells. This technique can therefore be used for the design of CMOS pass networks, with reduced switching activity, suitable for use in DSP hardware for the design of smaller and energy-efficient DSP processors. |
| Starting Page | 3327 |
| Ending Page | 3330 |
| File Size | 337914 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780362934 |
| ISSN | 15206149 |
| DOI | 10.1109/ICASSP.2000.860112 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-06-05 |
| Publisher Place | Turkey |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic circuits Switching circuits Digital signal processing Digital signal processing chips CMOS logic circuits Hardware Power dissipation Integrated circuit interconnections MOSFETs Energy consumption |
| Content Type | Text |
| Resource Type | Article |
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