NDLI: High-performance FPGA filters using sigma-delta modulation encoding

Content Provider	IEEE Xplore Digital Library
Author	Dick, C. Harris, F.
Copyright Year	1999
Description	Author affiliation: Xilinx Inc., San Jose, CA, USA (Dick, C.)
Abstract	This paper investigates an architectural option for constructing high sample-rate narrow-band single rate and multi-rate filters using Xilinx field programmable gate array (FPGA) technology. Sigma-delta modulation encoding is applied to the input data in order to effect a reduction in the precision of the arithmetic units in the filter. This is done without compromising the signal integrity within the band of interest. The implementation provides a significant savings in device logic resources in comparison to other techniques that provide the same functionality. The sigma-delta preprocessor is described and its implementation using XC4000 FPGAs is reported. The architecture of the reduced precision filter is presented and its FPGA realization described.
Starting Page	2123
Ending Page	2126
File Size	448645
Page Count	4
File Format	PDF
ISBN	0780350413
ISSN	15206149
DOI	10.1109/ICASSP.1999.758353
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-03-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Delta-sigma modulation Encoding Finite impulse response filter Dynamic range Narrowband Arithmetic Programmable logic arrays Logic devices Delay
Content Type	Text
Resource Type	Article

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