NDLI: Design of a time-slot-interchanger and other TDM bus interfacing issues

Content Provider	IEEE Xplore Digital Library
Author	Kessner, D.
Copyright Year	1998
Description	Author affiliation: Cyclades Corp., Fremont, CA, USA (Kessner, D.)
Abstract	This paper shows the design for an inexpensive time-slot-interchanger (TSI) for interchanging time-slot data between several time-division-multiplexed (TDM) busses. Additionally, many TDM bus-interfacing problems are discussed and solutions presented. The example TSI, design interfaces eight T1/E1 lines, although it is expandable in both the number of lines and speed. Routing of time-slot-data is done through a routing table stored in SRAM. It allows the data from one time slot to be routed to another time-slot on the same or different TDM bus. The TSI also has features that allow for the control of external buffers and non-TDM capable chips. It also allows for the generation of auxiliary frame sync signals for those difficult to interface chips. The TSI logic can be implemented in a <10K gate FPGA and small external Sync-SRAM- for a very low cost solution.
Starting Page	515
Ending Page	521
File Size	649291
Page Count	7
File Format	PDF
ISBN	0780343115
ISSN	1095323X
DOI	10.1109/AERO.1998.682218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-28
Publisher Place	Colorado
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Time division multiplexing Clocks Field programmable gate arrays Routing Random access memory Switches Signal generators Logic Costs Very high speed integrated circuits
Content Type	Text
Resource Type	Article
Subject	Aerospace Engineering Space and Planetary Science

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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