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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Young Uk Yim Curran, P.F. McDonald, J.F. |
| Copyright Year | 2006 |
| Description | Author affiliation: Rensselaer Polytech Inst., Troy (Young Uk Yim; Curran, P.F.; McDonald, J.F.) |
| Abstract | An 8-phase 20 GHz PLL has been designed for a serial transceiver. The PLL has a wide locking range from 10 GHz to 20 GHz with a phase noise of -112 dBc/Hz at 10 kHz offset. The PLL uses a four-stage ring oscillator that has a wide tuning range with a feedforward interpolation topology for coarse frequency tuning and a varactor diode load capacitance variation for fine frequency tuning. The PLL is fabricated in 0.13-mum SiGe BiCMOS technology. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 952171 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781424400027 |
| DOI | 10.1109/SARNOF.2006.4534766 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-03-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops Data communication Tuning Frequency Transceivers Phase noise Ring oscillators Interpolation Topology Varactors |
| Content Type | Text |
| Resource Type | Article |
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