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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Stevens, K. Ginosar, R. Rotem, S. |
| Copyright Year | 1999 |
| Description | Author affiliation: Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA (Stevens, K.) |
| Abstract | Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases. |
| Starting Page | 208 |
| Ending Page | 218 |
| File Size | 203670 |
| Page Count | 11 |
| File Format | |
| ISBN | 0769500315 |
| ISSN | 15228681 |
| DOI | 10.1109/ASYNC.1999.761535 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-04-21 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Timing Circuit synthesis Clocks Design automation Design methodology Asynchronous circuits Delay effects Delay estimation Radio access networks Very large scale integration |
| Content Type | Text |
| Resource Type | Article |
| Subject | Engineering |
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