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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cortadella, J. Kishinevsky, M. Kondratyev, A. Lavagno, L. Yakovlev, A. |
| Copyright Year | 1996 |
| Description | Author affiliation: Univ. Politecnica de Catalunya, Barcelona, Spain (Cortadella, J.) |
| Abstract | Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which happens when a pair of different states in an SG has the same binary encoding. A standard way to approach state coding conflicts is to add new state signals into the original specification in such a way that the original behaviour remains intact. Existing methods have not yet been able to provide such theoretical foundation for event insertion, that could yield efficient practical results when applied to large models. This paper aims at presenting such a general framework, which is based on two fundamental concepts. One is a region of states in an abstract labelled SG (called a Transition System). Regions correspond to places in the associated STG. The second concept is a speed-independence preserving set, which is strongly related to the implementability of the model in logic. Regions and their intersections offer "nice" structural properties that make them efficient "construction blocks" for event insertion. The application of our theory, through the software tool "petrify", to state graphs of large size has proved to be successful. |
| Starting Page | 36 |
| Ending Page | 47 |
| File Size | 1405252 |
| Page Count | 12 |
| File Format | |
| ISBN | 0818672986 |
| DOI | 10.1109/ASYNC.1996.494436 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-03-18 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Encoding Signal synthesis Circuit synthesis Asynchronous circuits Logic Application software Software tools Size control Signal resolution Hazards |
| Content Type | Text |
| Resource Type | Article |
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