NDLI: A structural approach for designing performance enhanced signal processors: a 1-MIPS GSM fullrate vocoder case study

Content Provider	IEEE Xplore Digital Library
Author	Weiss, M.H. Walther, U. Fettweis, G.P.
Copyright Year	1997
Description	Author affiliation: Mobile Commun. Syst., Tech. Univ. Dresden, Germany (Weiss, M.H.)
Abstract	Performance enhanced DSP (digital signal processor) architectures incorporate either datapath add-ons such as dual-MAC architectures or tailored datapaths such as Viterbi accelerators. Both strategies strongly influence the instruction set architecture (ISA). Since common ISAs are not designed for architectural enhancements, either a complete redesign is required or architectural enhancements cannot be fully exploited by the ISA. Taking the GSM fullrate vocoder as an example, a structural approach is presented to show how datapath add-ons or tailorizations can be applied to increase the DSP's performance. To efficiently utilize architectural enhancements we propose a modified VLIW (very long instruction word) ISA, called TVLIW (tagged VLIW). TVLIW combines both VLIW performance and DSP codewidth requirements. To demonstrate the applicability, we applied the TVLIW ISA to a highly pipelined quadruple-MAC architecture, incorporating only one dualport RAM and a 26-bit wide instruction word.
Starting Page	4085
Ending Page	4088
File Size	420033
Page Count	4
File Format	PDF
ISBN	0818679190
ISSN	15206149
DOI	10.1109/ICASSP.1997.604844
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-21
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal design Signal processing GSM Instruction sets Digital signal processing VLIW Vocoders Viterbi algorithm Algorithm design and analysis Transistors
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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