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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Oh, S. Garcia, D. |
| Copyright Year | 1994 |
| Description | Author affiliation: Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA (Oh, S.; Garcia, D.) |
| Abstract | A parallel decision feedback equalizer (DFE) implementation using residue number system (RNS) is considered When the DFE implementation for a system requires a wide input data width and high sampling rates, RNS provides a speed advantage over conventional approaches. This speed advantage can be obtained without an overall increase in hardware complexity. We present the results of our initial feasibility study implementing a DFE using RNS. A comparison of RNS and conventional approaches is given in terms of gate counts and gate delays.< |
| File Size | 369749 |
| File Format | |
| ISBN | 0780317750 |
| ISSN | 15206149 |
| DOI | 10.1109/ICASSP.1994.390024 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-04-19 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Decision feedback equalizers Hardware Signal processing algorithms Least squares approximation HDTV Digital signal processing Signal processing Digital filters Telephony Modems |
| Content Type | Text |
| Resource Type | Article |
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