NDLI: ASSYNT: efficient assembly code generation for digital signal processors starting from a data flowgraph

Content Provider	IEEE Xplore Digital Library
Author	Desmet, D. Genin, D.
Copyright Year	1993
Description	Author affiliation: EDC-Mentor Graphics Corp, Leuven, Belgium (Desmet, D.; Genin, D.)
Abstract	The authors describe the architecture of a code generator for digital signal processors, embedded in a data-flow-based specification environment. The data-flow-based specification and implementation techniques make it possible to generate highly efficient assembly code. Versions for TMS320C30 and TMS320C40 and DSP56000 currently exist. The automatic synthesis of high-level descriptions expressed in the signal flowgraph (SFG) can be guided by the user by means of implementation directives and external libraries. The authors discuss the internal data structures, based on a mixed control and data flowgraph, as well as the data-flow synthesis techniques used, involving scheduling, mapping, and memory management. Special attention is paid to the handling of hierarchical SFGs, pointer arithmetic, and the implementation of delay lines.<>
Starting Page	45
Ending Page	48
File Size	387731
Page Count	4
File Format	PDF
ISBN	0780374029
ISSN	15206149
DOI	10.1109/ICASSP.1993.319431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-04-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Assembly Signal generators Signal synthesis Digital signal processors Libraries Data structures Automatic control Memory management Arithmetic Delay lines
Content Type	Text
Resource Type	Article

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