NDLI: An area-efficient VLSI architecture for decoding of Reed-Solomon codes

Content Provider	IEEE Xplore Digital Library
Author	Jah-Ming Hsu Chin-Liang Wang
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Jah-Ming Hsu)
Abstract	This paper presents a new pipelined VLSI array for decoding Reed-Solomon (RS) codes. The architecture is designed based on the modified time-domain Berlekamp-Massey algorithm incorporated with the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder reaches an average decoding rate of one data symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.
Starting Page	3291
Ending Page	3294
File Size	373702
Page Count	4
File Format	PDF
ISBN	0780331923
ISSN	15206149
DOI	10.1109/ICASSP.1996.550580
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-05-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Reed-Solomon codes Error correction codes Time domain analysis Delay Iterative decoding Error correction Computer architecture HDTV Computational complexity
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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