NDLI: Timing error masking by exploiting operand value locality in SIMD architecture

Content Provider	IEEE Xplore Digital Library
Author	Jaehyeong Sim Jun-Seok Park Seungwook Paek Lee-Sup Kim
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. Eng., KAIST, Daejeon, South Korea (Jaehyeong Sim; Jun-Seok Park; Seungwook Paek; Lee-Sup Kim)
Abstract	A significant amount of energy is consumed by a voltage guardband to ensure error-free operations under the worsening PVT variations in modern processors. Circuit-level timing speculation has become a popular approach that increases energy efficiency by removing such guardband and tolerating occasional timing errors. However, SIMD processors suffer from a large throughput and energy efficiency loss induced by a conventional error correction mechanism which requires several extra cycles for each timing error. In this paper, we present an error masking scheme to eliminate the chances of performing the error correction. The error masking is done by allowing potential erroneous addition instructions to reuse the partial result of previous operations. We show that reuse can be applied to a large number of addition instructions by exploiting the observations that SIMD applications exhibit high levels of temporal operand value locality and operand value locality across SIMD lanes. Our implementation of the proposed masking scheme is augmented with the conventional pipeline logics. Simulation results verify that our scheme achieves up to 5.1% improvement in energy efficiency and 30% improvement in EDP (Energy-Delay-Product) over the baseline design.
Starting Page	90
Ending Page	96
File Size	1284176
Page Count	7
File Format	PDF
ISBN	9781479964925
DOI	10.1109/ICCD.2014.6974667
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-19
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Program processors Throughput Delays Adders Logic gates
Content Type	Text
Resource Type	Article

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