NDLI: Flipping modules to minimize maximum wire length

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Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

How to design a parallel computer

Liquid nitrogen CMOS for computer applications

Neural networks update

Design and test-the two sides of a coin

Logic design for a high performance mainframe computer-the HITAC M-880 processor

Architectural considerations for SF-core based microprocessor

Module generation for AND/XOR-fields (XPLAs)

A layout compaction algorithm with multiple grid constraints

Methods and algorithms for converting IC designs between incompatible design systems

Incremental synthesis for engineering changes

Concurrent resynthesis for network optimization

Dual global flow

Stafan algorithms for MOS circuits

Fast differential fault simulation by dynamic fault ordering

A fine grain architecture for parallel fault simulation

Partitioning sequential circuits for logic optimization

Redundancy identification and removal based on implicit state enumeration

Retiming of circuits with single phase transparent latches

Modeling of interconnection lines for simulation of VLSI circuits

Power play-fast dynamic power estimation based on logic simulation

Parallel event-driven waveform relaxation

A technique for generating efficient simulators

Designing self-testable cellular arrays

Concurrent error detection in array dividers by alternating input data

Testing of analog neural array-processor chips

Fault-tolerant model of neural computing

On-chip multiple superscalar processors with secondary cache memories

System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations

DesignFab: a methodology for ULSI microprocessor design

Implementation-independent model of an instruction set architecture using VHDL

Overview of the Monsoon project

The Monsoon interconnection network

Test and validation for Monsoon processing elements

An effective analog approach to Steiner routing

Performance-driven global routing for cell based ICs

Critical net routing

Synthesis of delay-insensitive circuits by refinement into atomic threads

Self-timed logic using current-sensing completion detection (CSCD)

Synthesis of asynchronous state machines using a local clock

Amdahl chip delay test system

Robust path delay-fault testability on dynamic CMOS circuits

Syndrome-based functional delay fault location in linear digital data-flow graphs

A data-driven architecture for distributed parallel processing

MPU: a N-tuple matching processor

Transitive closure and graph component labeling on realistic processor arrays based on reconfigurable mesh network

Decomposed arbiters for large crossbars with multi-queue input buffers

A compositional transformation for formal verification

Automatic derivation of FSM specification to implementation encoding

Design verification and reachability analysis using algebraic manipulation

Boolean satisfiability and equivalence checking using general binary decision diagrams

Power-down structures for BIST

A unique approach to built-in-self-test circuit design

New implementations, tools, and experiments for decreasing self-checking PLAs area overhead

A built-in self-testing approach for minimizing hardware overhead

CMOS processor circuit design in Hewlett-Packard's series 700 workstations

F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation

F-RISC/G: AlGaAs/GaAs HBT standard cell library

A mechanism for efficient context switching

A genetic algorithm for global improvement of macrocell layouts

I/O pad assignment based on the circuit structure

A provable near-optimal algorithm for the channel pin assignment problem

Design methodology for a MIPS compatible embedded control processor

Verification techniques for a MIPS compatible embedded control processor

The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications

Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II

Specifying system behavior in CPA

A formally verified system for logic synthesis

Aliasing probability in multiple input linear signature automata for q-ary symmetric errors

Reduced Hamming count and its aliasing probability

On the manifestation of faults to errors in signature analysis

Operation method in fuzzy set operation processor

A tag coprocessor architecture for symbolic languages

An efficient pattern match architecture for production systems using content-addressable memory

Object caching for performance in object-oriented systems

Early performance estimation of super scalar machine models

Interlock schemes for micropipelines: application to a self-timed rebound sorter

An adaptive hardware machine architecture and compiler for dynamic processor reconfiguration

FASTCHART-idea and implementation (virtual machine)

Mapping design knowledge from multiple representations

Synthesizing converters between finite state protocols

An integrated design environment for application specific integrated processor

Allocation of multiport memory with ports of different type in register transfer level synthesis

Random testability of redundant circuits

Logic synthesis of 100-percent testable logic networks

Fault tolerant VLSI design with functional block redundancy

Gigascale integration (GIS) in the 21st century

IBM AS/400 processor architecture and design methodology

VLSI design automation for the application system/400

IBM AS/400 processor technology

Logic synthesis of synchronous parallel controllers

SYNTEST: a method for high-level SYNthesis with self-TESTability

Accessibility analysis on data flow graph: an approach to design for testability

Design considerations for digital circuit interconnections in a multilayer printed circuit board

Fine-line printed circuit board for high-performance computer design

Fast capacitance extraction of general three-dimensional structures

A simulator for general purpose optical arrays

An optical multichip module

A GaAs receiver module for optoelectronic computing and interconnection

VLSI designs for high-speed Huffman decoder

BioSCAN: a VLSI-based system for biosequence analysis

VLSI implementation of a new block cipher

An optimal algorithm for spiral floorplan designs

Area optimization for higher order hierarchical floorplans

The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order

Flipping modules to minimize maximum wire length

High performance packaged electronics for the IBM ES9000 mainframe

IBM ES/9000 system architecture and hardware

Enhanced chip/package design for the IBM ES/9000

Design automation of test for the ES/9000 series processors

A comparison of redundant CORDIC rotation engines

A fast division algorithm for VLSI

High-speed VLSI arithmetic processor architectures using hybrid number representation

New classes of unidirectional error-detecting codes

Design and synthesis of self-checking VLSI circuits and systems

Design of a self-testing checker for Borden code

Technologies for rapid prototyping of multi-chip modules

Energy considerations in multichip-module based multiprocessors

The commercial realization of multi-chip modules quo vadimus

High-performance VLSI processor for robot inverse dynamics computation

A new O(n log n) scheduling heuristic for parallel decomposition of sparse matrices

A predictive parallel motion estimation algorithm for digital image processing

A multiprocessor architecture for circuit simulation

Three-level decomposition with application to PLDs

An algorithm for the multi-level minimization of Reed-Muller representations

Indentification of viable paths using binary decision diagrams

Optimal clocking of circular pipelines

Nimbus: An integrated display chip

IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3)

Implicit manipulation of equivalence classes using binary decision diagrams

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

Proceedings 1988 IEEE International Conference on Computer Design: VLSI

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